The pursuit of continuous scaling of electronic devices in the semiconductor\nindustry has led to two unintended but significant outcomes: a rapid increase in susceptibility\nto radiation induced errors, and an overall rise in power consumption. Operating under\nlow voltage to reduce power only aggravates radiation related reliability issues. The\nproposed ââ?¬Å?SEU Hardening Incorporating Extreme Low Power Bitcell Designââ?¬Â (SHIELD)\naddresses these two major concerns simultaneously. It is based on the concept of gating\nthe conventional cross-coupled inverters while introducing a novel ââ?¬Å?cut-offââ?¬Â network.\nThis creates redundant storage nodes and eliminates the internal feedback loop during\nradiation particle impact. The SHIELD bitcell tolerates upsets with charge deposits over\n1 pC. Simulations confirm its advantages in terms of leakage power, with more than twofold\nlower leakage currents than previous solutions when operated at a 700mV supply voltage in\na 65 nm process. To validate the bitcellââ?¬â?¢s robustness, several test cases and special concerns,\nincluding multiple node upsets (MNU) and half-select, are examined.
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